From: Pat Thoyts <patthoyts@users.sourceforge.net>
Date: Wed, 10 Oct 2018 20:55:03 +0000 (+0100)
Subject: Updated Makefile using common format
X-Git-Url: http://privyetmir.co.uk/gitweb.cgi?a=commitdiff_plain;h=HEAD;p=electronics%2Ftms-emulator

Updated Makefile using common format
---

diff --git a/Makefile b/Makefile
index 85e9745..210c8ee 100644
--- a/Makefile
+++ b/Makefile
@@ -1,29 +1,77 @@
-NAME=tms-emulator
-PROJECT=project
-SCHEMAS=tms-emulator.sch
+#
+# GEDA targets
+#
 
-update: $(NAME).net
+# Read the name and schema files from the GEDA project file:
+PROJECT=project
+NAME    := $(shell sed -n 's/^output-name //p' $(PROJECT))
+SCHEMAS := $(shell sed -n 's/^schematics //p' $(PROJECT))
+V := @
+Q := $(V:1=)
 
-$(NAME).net: $(SCHEMAS)
-	gsch2pcb --use-files $(PROJECT)
+QUIET_GSCH2PCB = $(Q:@=@echo   GSCH2PCB $@ &)gsch2pcb
+QUIET_GNETLIST = $(Q:@=@echo   GNETLIST $@ &)gnetlist
 
+pcb: $(NAME).net
 bom: $(NAME).bom
+drc: $(NAME).drc
+gerber: $(NAME).zip
+render: $(NAME).png
+pdf: $(NAME).pdf
 
-$(NAME).bom: $(SCHEMAS) attribs
-	gnetlist -g bom -o $@ $(SCHEMAS)
+$(NAME).net: $(SCHEMAS)
+	$(QUIET_GSCH2PCB) --use-files $(PROJECT)
 
-drc: $(SCHEMAS)
-	gnetlist -g drc2 -o /dev/stdout $^
+$(NAME).bom: $(SCHEMAS) attribs
+	$(QUIET_GNETLIST) -g bom -o $@ -- $(SCHEMAS)
 
-gerber: $(NAME).zip
+$(NAME).drc: $(SCHEMAS)
+	$(QUIET_GNETLIST) -g drc2 -o - -- $^
 
+# Use Hackvana style for SeeedStudio Fusion.
+# SeeedStudio Design for Manufacture documentation:
+#   https://statics3.seeedstudio.com/fusion/ebook/PCB+DFM+V1.0+.pdf
+# Minimum spacings:
+#   min trace width 4mil min trace spacing 4mil
+#   min space between trace and pour 8mil
+#   min space between vias 12mil
+#   min space between trace and PTH 12mil
+#   min annular ring 6mil
+#   min silk width 4mil
+#
+#   Top Layer $(NAME).gtl
+#   Top Solder Mask: $(NAME).gts
+#   Top Silkscreen: $(NAME).gto
+#   Top solderpaste: $(NAME).gtp
+#   Bottom Layer $(NAME).gbl
+#   Bottom Solder Mask: $(NAME).gbs
+#   Bottom Silkscreen: $(NAME).gbo
+#   Drills: $(NAME).txt
+#   Milling layer (outline): $(NAME).gm1 (Seeed state .GML)
+# We get this additional file
+#   Fabrication information: $(NAME).fab
+# and SeeedStudio appears to use this (at least the outline).
+#
 $(NAME).zip: $(NAME).pcb
-	rm -f gerber/* $@
+	$(RM) -f gerber/* $@
+	mkdir -p gerber
 	pcb -x gerber --gerberfile "gerber/$(NAME)" --name-style hackvana $(NAME).pcb
+	merge_drills.pl gerber/$(NAME)*.drl > gerber/$(NAME).txt
+	rm gerber/$(NAME)*.drl
 	zip -j $@ gerber/*
 
+$(NAME).png: $(NAME).pcb
+	pcbrender $^ $(NAME).png
+
+$(NAME).pdf: $(SCHEMAS)
+	gaf export --paper=iso_a4 --color --output=$@ $^
+
+check-names:
+	@echo PROJECT $(PROJECT)
+	@echo NAME $(NAME)
+	@echo SCHEMAS $(SCHEMAS)
+
 clean:
-	-rm $(NAME).bom
-	-rm $(NAME).new.pcb
+	-@$(RM) -f $(addprefix $(NAME), .bom .new.pcb .elf .hex)
 
 .PHONY: drc bom update clean gerber