From: Pat Thoyts Date: Fri, 12 Dec 2014 00:00:27 +0000 (+0000) Subject: Good board layout (fixed net by manually editing netlist). X-Git-Url: http://privyetmir.co.uk/gitweb.cgi?a=commitdiff_plain;h=8dda8339aa7b23113f0b13ce8a83e0b79ba4feaa;p=vetinari_clock Good board layout (fixed net by manually editing netlist). --- diff --git a/circuit_pth/vetinari.pcb b/circuit_pth/vetinari.pcb index 9b3eb64..acd8254 100644 --- a/circuit_pth/vetinari.pcb +++ b/circuit_pth/vetinari.pcb @@ -3,15 +3,15 @@ # To read pcb files, the pcb version (or the git source date) must be >= the file version FileVersion[20070407] -PCB["" 200000 100000] +PCB["Vetinari Clock" 200000 120000] Grid[10000.0 0 0 1] Cursor[0 20000 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[1000 1000 1000 1000 1500 1000] -Flags("nameonpcb,uniquename,clearnew") -Groups("1,c:2:3:4:5:6,s:7:8") +Flags("nameonpcb,uniquename,clearnew,snappin") +Groups("1,c:2,s:3") Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"] Symbol[' ' 1800] @@ -788,7 +788,78 @@ Symbol['~' 1200] ) Attribute("PCB::grid::unit" "mil") -Element["" "DIP-14-300" "U1" "unknown" 40000 50000 -21000 -41500 0 100 ""] +Element["" "R025" "R3" "68R" 70000 90000 0 -5000 0 100 ""] +( + Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"] + Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"] + ElementLine [10000 -5000 30000 -5000 2000] + ElementLine [30000 -5000 30000 5000 2000] + ElementLine [30000 5000 10000 5000 2000] + ElementLine [10000 5000 10000 -5000 2000] + ElementLine [0 0 10000 0 2000] + ElementLine [30000 0 40000 0 2000] + + ) + +Element["" "R025" "R2" "68R" 70000 80000 0 -5000 0 100 ""] +( + Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"] + Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"] + ElementLine [10000 -5000 30000 -5000 2000] + ElementLine [30000 -5000 30000 5000 2000] + ElementLine [30000 5000 10000 5000 2000] + ElementLine [10000 5000 10000 -5000 2000] + ElementLine [0 0 10000 0 2000] + ElementLine [30000 0 40000 0 2000] + + ) + +Element["" "ACY500" "R1" "47K" 110000 70000 0 -40000 0 100 ""] +( + Pin[0 0 5500 3000 6100 3000 "1" "1" "square"] + Pin[0 -50000 5500 3000 6100 3000 "2" "2" ""] + ElementLine [0 -12500 0 0 1000] + ElementLine [0 -50000 0 -37500 1000] + ElementLine [-4100 -37500 -4100 -12500 1000] + ElementLine [-4100 -37500 4100 -37500 1000] + ElementLine [4100 -37500 4100 -12500 1000] + ElementLine [-4100 -12500 4100 -12500 1000] + + ) + +Element["" "RCY100" "X1" "32768_Hz" 75000 40000 15000 10000 3 100 ""] +( + Pin[0 0 6000 3000 6600 3000 "1" "1" "square"] + Pin[0 10000 6000 3000 6600 3000 "2" "2" ""] + ElementArc [0 5000 10000 10000 270 360 1000] + + ) + +Element["" "ACY100" "C2" "100nF" 70745 29880 -10000 0 1 100 ""] +( + Pin[0 0 5500 3000 6100 3000 "1" "1" "square"] + Pin[0 -10000 5500 3000 6100 3000 "2" "2" ""] + ElementLine [0 -2500 0 0 1000] + ElementLine [0 -10000 0 -7500 1000] + ElementLine [-800 -7500 -800 -2500 1000] + ElementLine [-800 -7500 800 -7500 1000] + ElementLine [800 -7500 800 -2500 1000] + ElementLine [-800 -2500 800 -2500 1000] + + ) + +Element["" "RCY100P" "C1" "10uF" 90000 20000 10000 -5000 3 100 ""] +( + Pin[0 0 6000 3000 6600 3000 "+" "1" "square"] + Pin[0 10000 6000 3000 6600 3000 "-" "2" ""] + ElementLine [0 -11000 0 -7000 1000] + ElementLine [-2000 -9000 2000 -9000 1000] + ElementLine [0 17000 0 21000 1000] + ElementArc [0 5000 10000 10000 270 360 1000] + + ) + +Element["" "DIP-14-300" "U1" "unknown" 40000 60000 -21000 -41500 0 100 ""] ( Pin[-15000 -30000 6000 2000 8000 3500 "DVCC" "1" ""] Pin[-15000 -20000 6000 2000 8000 3500 "P1.0/TA0CLK/ACLK/CA0" "2" ""] @@ -842,7 +913,7 @@ Element["" "DIP-14-300" "U1" "unknown" 40000 50000 -21000 -41500 0 100 ""] ) -Element["" "1x4PIN" " + - TEST RST" "POWER" 170000 10000 11811 -6063 3 100 ""] +Element["" "1x4PIN" "CONN1" "POWER" 170000 20000 11811 -6063 3 100 ""] ( Pin[0 30000 8100 3937 8494 4600 "4" "4" ""] Pin[0 20000 8100 3937 8494 4600 "3" "3" ""] @@ -855,7 +926,7 @@ Element["" "1x4PIN" " + - TEST RST" "POWER" 170000 10000 11811 -6063 3 100 " ) -Element["" "1x2PIN" "CLOCK" "COIL" 170000 70000 11811 -3937 3 100 ""] +Element["" "1x2PIN" "CONN2" "COIL" 170000 80000 11811 -3937 3 100 ""] ( Pin[0 0 8100 3937 8494 4600 "1" "1" "square"] Pin[0 10000 8100 3937 8494 4600 "2" "2" ""] @@ -866,36 +937,10 @@ Element["" "1x2PIN" "CLOCK" "COIL" 170000 70000 11811 -3937 3 100 ""] ) -Element["" "R025" "R3" "68R" 70000 70000 0 -5000 0 100 ""] -( - Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"] - Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"] - ElementLine [10000 -5000 30000 -5000 2000] - ElementLine [30000 -5000 30000 5000 2000] - ElementLine [30000 5000 10000 5000 2000] - ElementLine [10000 5000 10000 -5000 2000] - ElementLine [0 0 10000 0 2000] - ElementLine [30000 0 40000 0 2000] - - ) - -Element["" "R025" "R2" "68R" 70000 80000 0 -5000 0 100 ""] -( - Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"] - Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"] - ElementLine [10000 -5000 30000 -5000 2000] - ElementLine [30000 -5000 30000 5000 2000] - ElementLine [30000 5000 10000 5000 2000] - ElementLine [10000 5000 10000 -5000 2000] - ElementLine [0 0 10000 0 2000] - ElementLine [30000 0 40000 0 2000] - - ) - -Element["" "ALF500" "D2" "1N4148" 150000 70000 -25000 0 1 100 ""] +Element["" "DIODE_LAY-500" "D2" "1N4148" 150000 80000 -25000 0 1 100 ""] ( Pin[0 0 8000 3000 8600 2000 "1" "1" "square"] - Pin[0 -50000 8000 3000 8600 2000 "2" "2" ""] + Pin[0 -50000 8000 3000 8600 2000 "2" "2" "selected"] ElementLine [0 -16600 0 0 1000] ElementLine [0 -50000 0 -33400 1000] ElementLine [0 -16600 -8300 -33400 1000] @@ -905,49 +950,7 @@ Element["" "ALF500" "D2" "1N4148" 150000 70000 -25000 0 1 100 ""] ) -Element["" "ACY500" "R1" "47K" 110000 60000 0 4100 2 100 ""] -( - Pin[0 0 5500 3000 6100 3000 "1" "1" "square"] - Pin[0 -50000 5500 3000 6100 3000 "2" "2" ""] - ElementLine [0 -12500 0 0 1000] - ElementLine [0 -50000 0 -37500 1000] - ElementLine [-4100 -37500 -4100 -12500 1000] - ElementLine [-4100 -37500 4100 -37500 1000] - ElementLine [4100 -37500 4100 -12500 1000] - ElementLine [-4100 -12500 4100 -12500 1000] - - ) - -Element["" "RCY100" "X1" "32768_Hz" 75000 40000 -10000 5000 1 100 ""] -( - Pin[0 0 6000 3000 6600 3000 "1" "1" "square"] - Pin[0 -10000 6000 3000 6600 3000 "2" "2" ""] - ElementArc [0 -5000 10000 10000 90 360 1000] - - ) - -Element["" "pad_thru" "" "pad_thru" 120000 60000 -3938 -11811 0 100 ""] -( - Pin[0 0 6100 3937 6494 3500 "1" "1" ""] - ElementArc [0 0 4000 4000 0 360 1000] - - ) - -Element["" "pad_thru" "" "pad_thru" 100000 30000 -3938 -11811 0 100 ""] -( - Pin[0 0 6100 3937 6494 3500 "1" "1" ""] - ElementArc [0 0 4000 4000 0 360 1000] - - ) - -Element["" "pad_thru" "" "pad_thru" 100000 50000 -3938 -11811 0 100 ""] -( - Pin[0 0 6100 3937 6494 3500 "1" "1" ""] - ElementArc [0 0 4000 4000 0 360 1000] - - ) - -Element["" "ALF600" "D1" "1N4148" 140000 80000 -30000 0 1 100 ""] +Element["" "DIODE_LAY-600" "D1" "1N4148" 140000 90000 -30000 0 1 100 ""] ( Pin[0 0 8000 3000 8600 2000 "1" "1" "square"] Pin[0 -60000 8000 3000 8600 2000 "2" "2" ""] @@ -959,78 +962,77 @@ Element["" "ALF600" "D1" "1N4148" 140000 80000 -30000 0 1 100 ""] ElementLine [-10000 -20000 10000 -20000 1000] ) -Rat[170000 20000 0 170000 80000 0 ""] -Rat[170000 80000 0 170000 70000 0 ""] -Rat[75000 30000 0 75000 40000 0 ""] -Rat[70000 80000 0 70000 70000 0 ""] Layer(1 "top") ( - Line[25000 20000 10000 20000 1000 2000 "clearline"] - Line[10000 20000 10000 10000 1000 2000 "clearline"] - Line[10000 10000 170000 10000 1000 2000 "clearline"] - Line[55000 70000 70000 70000 1000 2000 "clearline"] + Line[25000 30000 10000 30000 1000 2000 "clearline"] + Line[10000 30000 10000 20000 1000 2000 "clearline"] Line[55000 80000 70000 80000 1000 2000 "clearline"] - Line[55000 20000 170000 20000 1000 2000 "clearline"] - Line[55000 30000 75000 30000 1000 2000 "clearline"] + Line[55000 90000 70000 90000 1000 2000 "clearline"] Line[55000 40000 75000 40000 1000 2000 "clearline"] - Line[110000 70000 170000 70000 1000 2000 "clearline"] - Line[170000 40000 120000 40000 1000 2000 "clearline"] - Line[120000 40000 120000 60000 1000 2000 "clearline"] - Line[120000 60000 55000 60000 1000 2000 "clearline"] - Line[170000 30000 100000 30000 1000 2000 "clearline"] - Line[100000 30000 100000 50000 1000 2000 "clearline"] - Line[100000 50000 55000 50000 1000 2000 "clearline"] + Line[55000 50000 75000 50000 1000 2000 "clearline"] Line[110000 80000 170000 80000 1000 2000 "clearline"] + Line[100000 90000 170000 90000 1000 2000 "clearline"] + Line[170000 30000 55000 30000 1000 2000 "clearline"] + Line[10000 20000 170000 20000 1000 2000 "clearline"] + Line[170000 40000 100000 40000 1000 2000 "clearline"] + Line[100000 40000 100000 60000 1000 2000 "clearline"] + Line[100000 60000 55000 60000 1000 2000 "clearline"] + Line[55000 70000 120000 70000 1000 2000 "clearline"] + Line[120000 70000 120000 50000 1000 2000 "clearline"] + Line[120000 50000 170000 50000 1000 2000 "clearline"] ) -Layer(2 "ground") +Layer(2 "bottom") ( ) -Layer(3 "signal2") -( -) -Layer(4 "signal3") -( -) -Layer(5 "power") -( -) -Layer(6 "bottom") -( -) -Layer(7 "outline") -( -) -Layer(8 "spare") +Layer(3 "outline") ( + Polygon("clearpoly") + ( + [0 0] [200000 0] [200000 120000] [0 120000] + ) ) -Layer(9 "silk") +Layer(4 "silk") ( ) -Layer(10 "silk") +Layer(5 "silk") ( - Text[10000 90000 0 100 "Vetinari's Clock v1.0" "clearline"] + Text[120000 100000 0 100 "Vetinari's Clock v1.0" "clearline"] + Text[90000 50000 0 100 "X" "clearline"] + Text[90000 40000 0 100 "X" "clearline"] ) NetList() ( Net("CLKN" "(unknown)") ( Connect("CONN2-2") - Connect("D2-2") - Connect("R2-2") + Connect("D1-1") + Connect("R3-2") ) Net("CLKP" "(unknown)") ( Connect("CONN2-1") - Connect("D1-2") - Connect("R3-2") + Connect("D2-1") + Connect("R2-2") ) Net("GND" "(unknown)") ( + Connect("C1-2") + Connect("C2-1") Connect("CONN1-2") - Connect("D1-1") - Connect("D2-1") + Connect("D1-2") + Connect("D2-2") Connect("U1-14") ) + Net("P1.6" "(unknown)") + ( + Connect("R3-1") + Connect("U1-8") + ) + Net("P1.7" "(unknown)") + ( + Connect("R2-1") + Connect("U1-9") + ) Net("RST" "(unknown)") ( Connect("CONN1-4") @@ -1043,53 +1045,45 @@ NetList() Connect("U1-11") ) Net("unnamed_net1" "(unknown)") - ( - Connect("U1-13") - Connect("X1-1") - ) - Net("unnamed_net2" "(unknown)") - ( - Connect("U1-12") - Connect("X1-2") - ) - Net("unnamed_net3" "(unknown)") - ( - Connect("R2-1") - Connect("U1-9") - ) - Net("unnamed_net4" "(unknown)") - ( - Connect("R3-1") - Connect("U1-8") - ) - Net("unnamed_net5" "(unknown)") ( Connect("U1-2") ) - Net("unnamed_net6" "(unknown)") + Net("unnamed_net2" "(unknown)") ( Connect("U1-3") ) - Net("unnamed_net7" "(unknown)") + Net("unnamed_net3" "(unknown)") ( Connect("U1-4") ) - Net("unnamed_net8" "(unknown)") + Net("unnamed_net4" "(unknown)") ( Connect("U1-5") ) - Net("unnamed_net9" "(unknown)") + Net("unnamed_net5" "(unknown)") ( Connect("U1-6") ) - Net("unnamed_net10" "(unknown)") + Net("unnamed_net6" "(unknown)") ( Connect("U1-7") ) Net("Vcc" "(unknown)") ( + Connect("C1-1") + Connect("C2-2") Connect("CONN1-1") Connect("R1-2") Connect("U1-1") ) + Net("XIN" "(unknown)") + ( + Connect("U1-13") + Connect("X1-1") + ) + Net("XOUT" "(unknown)") + ( + Connect("U1-12") + Connect("X1-2") + ) )