From: Pat Thoyts Date: Sat, 6 Dec 2014 18:09:08 +0000 (+0000) Subject: Added gschem schematic with a stripboard pcb layout as implemented. X-Git-Url: http://privyetmir.co.uk/gitweb.cgi?a=commitdiff_plain;h=664d7d632965be09a4c89ccbba0eaa581fdba695;p=vetinari_clock Added gschem schematic with a stripboard pcb layout as implemented. --- diff --git a/circuit_pth/Makefile b/circuit_pth/Makefile new file mode 100644 index 0000000..9c1de38 --- /dev/null +++ b/circuit_pth/Makefile @@ -0,0 +1,20 @@ +NAME = vetinari +SCHEMA_FILES = vetinari.sch + +netlist: $(NAME).net +bom: $(NAME).bom + +$(NAME).net: $(SCHEMA_FILES) + gsch2pcb --use-files $(NAME).project + +$(NAME).bom: $(SCHEMA_FILES) + gnetlist -g partslist3 -o $@ $^ + +drc: $(SCHEMA_FILES) + gnetlist -g drc2 -o /dev/stdout $^ + +clean: + -rm $(NAME).bom + -rm $(NAME).new.pcb + +.PHONY: drc bom update clean diff --git a/circuit_pth/gafrc b/circuit_pth/gafrc new file mode 100644 index 0000000..ec84c14 --- /dev/null +++ b/circuit_pth/gafrc @@ -0,0 +1,2 @@ +(component-library "./symbols") + diff --git a/circuit_pth/symbols/MSP430G2231.sym b/circuit_pth/symbols/MSP430G2231.sym new file mode 100644 index 0000000..d8b935a --- /dev/null +++ b/circuit_pth/symbols/MSP430G2231.sym @@ -0,0 +1,178 @@ +v 20130925 2 +P 100 2900 400 2900 1 0 0 +{ +T 300 2950 5 8 1 1 0 6 1 +pinnumber=1 +T 300 2850 5 8 0 1 0 8 1 +pinseq=1 +T 450 2900 9 8 1 1 0 0 1 +pinlabel=DVCC +T 450 2900 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=2 +T 300 2450 5 8 0 1 0 8 1 +pinseq=2 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=P1.0/TA0CLK/ACLK/CA0 +T 450 2500 5 8 0 1 0 2 1 +pintype=io +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=3 +T 300 2050 5 8 0 1 0 8 1 +pinseq=3 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=P1.1/TA0.0/CA1 +T 450 2100 5 8 0 1 0 2 1 +pintype=io +} +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=4 +T 300 1650 5 8 0 1 0 8 1 +pinseq=4 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=P1.2/TA0.1/CA2 +T 450 1700 5 8 0 1 0 2 1 +pintype=io +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=5 +T 300 1250 5 8 0 1 0 8 1 +pinseq=5 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=P1.3/CAOUT/CA3 +T 450 1300 5 8 0 1 0 2 1 +pintype=io +} +P 100 900 400 900 1 0 0 +{ +T 300 950 5 8 1 1 0 6 1 +pinnumber=6 +T 300 850 5 8 0 1 0 8 1 +pinseq=6 +T 450 900 9 8 1 1 0 0 1 +pinlabel=P1.4/SMCLK/CA4/TCK +T 450 900 5 8 0 1 0 2 1 +pintype=io +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=7 +T 300 450 5 8 0 1 0 8 1 +pinseq=7 +T 450 500 9 8 1 1 0 0 1 +pinlabel=P1.5/TA0.0/A5/SCLK/TMS +T 450 500 5 8 0 1 0 2 1 +pintype=io +} +P 4200 2900 3900 2900 1 0 0 +{ +T 4000 2950 5 8 1 1 0 0 1 +pinnumber=14 +T 4000 2850 5 8 0 1 0 2 1 +pinseq=8 +T 3850 2900 9 8 1 1 0 6 1 +pinlabel=DVSS +T 3850 2900 5 8 0 1 0 8 1 +pintype=pwr +} +P 4200 2500 3900 2500 1 0 0 +{ +T 4000 2550 5 8 1 1 0 0 1 +pinnumber=13 +T 4000 2450 5 8 0 1 0 2 1 +pinseq=9 +T 3850 2500 9 8 1 1 0 6 1 +pinlabel=XIN/P2.6/TA0.1 +T 3850 2500 5 8 0 1 0 8 1 +pintype=io +} +P 4200 2100 3900 2100 1 0 0 +{ +T 4000 2150 5 8 1 1 0 0 1 +pinnumber=12 +T 4000 2050 5 8 0 1 0 2 1 +pinseq=10 +T 3850 2100 9 8 1 1 0 6 1 +pinlabel=XOUT/P2.7 +T 3850 2100 5 8 0 1 0 8 1 +pintype=io +} +P 4200 1700 3900 1700 1 0 0 +{ +T 4000 1750 5 8 1 1 0 0 1 +pinnumber=11 +T 4000 1650 5 8 0 1 0 2 1 +pinseq=11 +T 3850 1700 9 8 1 1 0 6 1 +pinlabel=TEST/SBWTCK +T 3850 1700 5 8 0 1 0 8 1 +pintype=in +} +P 4200 1300 3900 1300 1 0 0 +{ +T 4000 1350 5 8 1 1 0 0 1 +pinnumber=10 +T 4000 1250 5 8 0 1 0 2 1 +pinseq=12 +T 3850 1300 9 8 1 1 0 6 1 +pinlabel=\_RST\_/NMI/SBWTDIO +T 3850 1300 5 8 0 1 0 8 1 +pintype=io +} +P 4200 900 3900 900 1 0 0 +{ +T 4000 950 5 8 1 1 0 0 1 +pinnumber=9 +T 4000 850 5 8 0 1 0 2 1 +pinseq=13 +T 3850 900 9 8 1 1 0 6 1 +pinlabel=P1.7/CAOUT/CA7/TDO/TDI +T 3850 900 5 8 0 1 0 8 1 +pintype=io +} +P 4200 500 3900 500 1 0 0 +{ +T 4000 550 5 8 1 1 0 0 1 +pinnumber=8 +T 4000 450 5 8 0 1 0 2 1 +pinseq=14 +T 3850 400 9 8 1 1 0 6 1 +pinlabel=P1.6/TA0.1/CA6/TDI/TCLK +T 3850 500 5 8 0 1 0 8 1 +pintype=io +} +B 400 100 3500 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 3900 3400 8 10 1 1 0 6 1 +refdes=U? +T 400 3400 9 10 1 0 0 0 1 +MSP430G2x11 +T 400 3600 5 10 0 0 0 0 1 +device=MSP430G2x11IPW14 +T 400 3800 5 10 0 0 0 0 1 +footprint=TSSOP14 +T 400 4000 5 10 0 0 0 0 1 +author=Evgeny Ivanov +T 400 4200 5 10 0 0 0 0 1 +documentation=www.ti.com/product/msp430g2231 +T 400 4400 5 10 0 0 0 0 1 +description=MSP430 MCU +T 400 4600 5 10 0 0 0 0 1 +numslots=0 +T 400 4800 5 10 0 0 0 0 1 +dist-license=GPL +T 400 5000 5 10 0 0 0 0 1 +use-license=unlimited +T 400 5200 5 10 0 0 0 0 1 +comment=generated with tragesym diff --git a/circuit_pth/vetinari.pcb b/circuit_pth/vetinari.pcb new file mode 100644 index 0000000..9b3eb64 --- /dev/null +++ b/circuit_pth/vetinari.pcb @@ -0,0 +1,1095 @@ +# release: pcb 20110918 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20070407] + +PCB["" 200000 100000] + +Grid[10000.0 0 0 1] +Cursor[0 20000 0.000000] +PolyArea[200000000.000000] +Thermal[0.500000] +DRC[1000 1000 1000 1000 1500 1000] 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1000 5000 800] +) +Symbol['%' 1200] +( + SymbolLine[0 1500 0 2000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 1500 800] + SymbolLine[1500 1500 1500 2000 800] + SymbolLine[1000 2500 1500 2000 800] + SymbolLine[500 2500 1000 2500 800] + SymbolLine[0 2000 500 2500 800] + SymbolLine[0 5000 4000 1000 800] + SymbolLine[3500 5000 4000 4500 800] + SymbolLine[4000 4000 4000 4500 800] + SymbolLine[3500 3500 4000 4000 800] + SymbolLine[3000 3500 3500 3500 800] + SymbolLine[2500 4000 3000 3500 800] + SymbolLine[2500 4000 2500 4500 800] + SymbolLine[2500 4500 3000 5000 800] + SymbolLine[3000 5000 3500 5000 800] +) +Symbol['&' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 3500 1500 2000 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[1000 5000 2000 4000 800] + SymbolLine[0 2500 2500 5000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 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SymbolLine[1000 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 5000 800] + SymbolLine[2000 3500 2500 3000 800] + SymbolLine[2500 3000 3000 3000 800] + SymbolLine[3000 3000 3500 3500 800] + SymbolLine[3500 3500 3500 5000 800] + SymbolLine[0 3000 500 3500 800] +) +Symbol['n' 1200] +( + SymbolLine[500 3500 500 5000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[1000 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 5000 800] + SymbolLine[0 3000 500 3500 800] +) +Symbol['o' 1200] +( + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['p' 1200] +( + SymbolLine[500 3500 500 6500 800] + SymbolLine[0 3000 500 3500 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[1000 3000 2000 3000 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[2500 3500 2500 4500 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[1000 5000 2000 5000 800] + SymbolLine[500 4500 1000 5000 800] +) +Symbol['q' 1200] +( + SymbolLine[2000 3500 2000 6500 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] +) +Symbol['r' 1200] +( + SymbolLine[500 3500 500 5000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[1000 3000 2000 3000 800] + SymbolLine[0 3000 500 3500 800] +) +Symbol['s' 1200] +( + SymbolLine[500 5000 2000 5000 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[2000 4000 2500 4500 800] + SymbolLine[500 4000 2000 4000 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 2000 3000 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['t' 1000] +( + SymbolLine[500 1000 500 4500 800] + SymbolLine[500 4500 1000 5000 800] + SymbolLine[0 2500 1000 2500 800] +) +Symbol['u' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 3000 2000 4500 800] +) +Symbol['v' 1200] +( + SymbolLine[0 3000 1000 5000 800] + SymbolLine[2000 3000 1000 5000 800] +) +Symbol['w' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[1000 5000 1500 4500 800] + SymbolLine[1500 3000 1500 4500 800] + SymbolLine[1500 4500 2000 5000 800] + SymbolLine[2000 5000 2500 5000 800] + SymbolLine[2500 5000 3000 4500 800] + SymbolLine[3000 3000 3000 4500 800] +) +Symbol['x' 1200] +( + SymbolLine[0 3000 2000 5000 800] + SymbolLine[0 5000 2000 3000 800] +) +Symbol['y' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[2000 3000 2000 6000 800] + SymbolLine[1500 6500 2000 6000 800] + SymbolLine[500 6500 1500 6500 800] + SymbolLine[0 6000 500 6500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] +) +Symbol['z' 1200] +( + SymbolLine[0 3000 2000 3000 800] + SymbolLine[0 5000 2000 3000 800] + SymbolLine[0 5000 2000 5000 800] +) +Symbol['{' 1200] +( + SymbolLine[500 1500 1000 1000 800] + SymbolLine[500 1500 500 2500 800] + SymbolLine[0 3000 500 2500 800] + SymbolLine[0 3000 500 3500 800] + SymbolLine[500 3500 500 4500 800] + SymbolLine[500 4500 1000 5000 800] +) +Symbol['|' 1200] +( + SymbolLine[0 1000 0 5000 800] +) +Symbol['}' 1200] +( + SymbolLine[0 1000 500 1500 800] + SymbolLine[500 1500 500 2500 800] + SymbolLine[500 2500 1000 3000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[500 3500 500 4500 800] + SymbolLine[0 5000 500 4500 800] +) +Symbol['~' 1200] +( + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1000 3000 800] + SymbolLine[1000 3000 1500 3500 800] + SymbolLine[1500 3500 2000 3500 800] + SymbolLine[2000 3500 2500 3000 800] +) +Attribute("PCB::grid::unit" "mil") + +Element["" "DIP-14-300" "U1" "unknown" 40000 50000 -21000 -41500 0 100 ""] +( + Pin[-15000 -30000 6000 2000 8000 3500 "DVCC" "1" ""] + Pin[-15000 -20000 6000 2000 8000 3500 "P1.0/TA0CLK/ACLK/CA0" "2" ""] + Pin[-15000 -10000 6000 2000 8000 3500 "P1.1/TA0.0/CA1" "3" ""] + Pin[-15000 0 6000 2000 8000 3500 "P1.2/TA0.1/CA2" "4" ""] + Pin[-15000 10000 6000 2000 8000 3500 "P1.3/CAOUT/CA3" "5" ""] + Pin[-15000 20000 6000 2000 8000 3500 "P1.4/SMCLK/CA4/TCK" "6" ""] + Pin[-15000 30000 6000 2000 8000 3500 "P1.5/TA0.0/A5/SCLK/TMS" "7" ""] + Pin[15000 30000 6000 2000 8000 3500 "P1.6/TA0.1/CA6/TDI/TCLK" "8" ""] + Pin[15000 20000 6000 2000 8000 3500 "P1.7/CAOUT/CA7/TDO/TDI" "9" ""] + Pin[15000 10000 6000 2000 8000 3500 "_RST_/NMI/SBWTDIO" "10" ""] + Pin[15000 0 6000 2000 8000 3500 "TEST/SBWTCK" "11" ""] + Pin[15000 -10000 6000 2000 8000 3500 "XOUT/P2.7" "12" ""] + Pin[15000 -20000 6000 2000 8000 3500 "XIN/P2.6/TA0.1" "13" ""] + Pin[15000 -30000 6000 2000 8000 3500 "DVSS" "14" ""] + Pad[-16500 -30000 -13500 -30000 6000 2000 8000 "DVCC" "1" "octagon"] + Pad[-16500 -30000 -13500 -30000 6000 2000 8000 "DVCC" "1" "onsolder,octagon"] + Pad[-16500 -20000 -13500 -20000 6000 2000 8000 "P1.0/TA0CLK/ACLK/CA0" "2" "octagon"] + Pad[-16500 -20000 -13500 -20000 6000 2000 8000 "P1.0/TA0CLK/ACLK/CA0" "2" "onsolder,octagon"] + Pad[-16500 -10000 -13500 -10000 6000 2000 8000 "P1.1/TA0.0/CA1" "3" "octagon"] + Pad[-16500 -10000 -13500 -10000 6000 2000 8000 "P1.1/TA0.0/CA1" "3" "onsolder,octagon"] + Pad[-16500 0 -13500 0 6000 2000 8000 "P1.2/TA0.1/CA2" "4" "octagon"] + Pad[-16500 0 -13500 0 6000 2000 8000 "P1.2/TA0.1/CA2" "4" "onsolder,octagon"] + Pad[-16500 10000 -13500 10000 6000 2000 8000 "P1.3/CAOUT/CA3" "5" "octagon"] + Pad[-16500 10000 -13500 10000 6000 2000 8000 "P1.3/CAOUT/CA3" "5" "onsolder,octagon"] + Pad[-16500 20000 -13500 20000 6000 2000 8000 "P1.4/SMCLK/CA4/TCK" "6" "octagon"] + Pad[-16500 20000 -13500 20000 6000 2000 8000 "P1.4/SMCLK/CA4/TCK" "6" "onsolder,octagon"] + Pad[-16500 30000 -13500 30000 6000 2000 8000 "P1.5/TA0.0/A5/SCLK/TMS" "7" "octagon"] + Pad[-16500 30000 -13500 30000 6000 2000 8000 "P1.5/TA0.0/A5/SCLK/TMS" "7" "onsolder,octagon"] + Pad[13500 30000 16500 30000 6000 2000 8000 "P1.6/TA0.1/CA6/TDI/TCLK" "8" "octagon,edge2"] + Pad[13500 30000 16500 30000 6000 2000 8000 "P1.6/TA0.1/CA6/TDI/TCLK" "8" "onsolder,octagon,edge2"] + Pad[13500 20000 16500 20000 6000 2000 8000 "P1.7/CAOUT/CA7/TDO/TDI" "9" "octagon,edge2"] + Pad[13500 20000 16500 20000 6000 2000 8000 "P1.7/CAOUT/CA7/TDO/TDI" "9" "onsolder,octagon,edge2"] + Pad[13500 10000 16500 10000 6000 2000 8000 "_RST_/NMI/SBWTDIO" "10" "octagon,edge2"] + Pad[13500 10000 16500 10000 6000 2000 8000 "_RST_/NMI/SBWTDIO" "10" "onsolder,octagon,edge2"] + Pad[13500 0 16500 0 6000 2000 8000 "TEST/SBWTCK" "11" "octagon,edge2"] + Pad[13500 0 16500 0 6000 2000 8000 "TEST/SBWTCK" "11" "onsolder,octagon,edge2"] + Pad[13500 -10000 16500 -10000 6000 2000 8000 "XOUT/P2.7" "12" "octagon,edge2"] + Pad[13500 -10000 16500 -10000 6000 2000 8000 "XOUT/P2.7" "12" "onsolder,octagon,edge2"] + Pad[13500 -20000 16500 -20000 6000 2000 8000 "XIN/P2.6/TA0.1" "13" "octagon,edge2"] + Pad[13500 -20000 16500 -20000 6000 2000 8000 "XIN/P2.6/TA0.1" "13" "onsolder,octagon,edge2"] + Pad[13500 -30000 16500 -30000 6000 2000 8000 "DVSS" "14" "octagon,edge2"] + Pad[13500 -30000 16500 -30000 6000 2000 8000 "DVSS" "14" "onsolder,octagon,edge2"] + ElementLine [-21000 -34500 -21000 34500 1000] + ElementLine [-21000 34500 21000 34500 1000] + ElementLine [21000 34500 21000 -34500 1000] + ElementLine [21000 -34500 5250 -34500 1000] + ElementLine [5250 -34500 0 -29250 1000] + ElementLine [0 -29250 -5250 -34500 1000] + ElementLine [-5250 -34500 -21000 -34500 1000] + + ) + +Element["" "1x4PIN" " + - TEST RST" "POWER" 170000 10000 11811 -6063 3 100 ""] +( + Pin[0 30000 8100 3937 8494 4600 "4" "4" ""] + Pin[0 20000 8100 3937 8494 4600 "3" "3" ""] + Pin[0 10000 8100 3937 8494 4600 "2" "2" ""] + Pin[0 0 8100 3937 8494 4600 "1" "1" "square"] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 35000 1000] + ElementLine [-5000 35000 5000 35000 1000] + ElementLine [-5000 -5000 -5000 35000 1000] + + ) + +Element["" "1x2PIN" "CLOCK" "COIL" 170000 70000 11811 -3937 3 100 ""] +( + Pin[0 0 8100 3937 8494 4600 "1" "1" "square"] + Pin[0 10000 8100 3937 8494 4600 "2" "2" ""] + ElementLine [-4921 -4921 4921 -4921 1000] + ElementLine [4921 -4921 4921 14764 1000] + ElementLine [-4921 14764 4921 14764 1000] + ElementLine [-4921 -4921 -4921 14764 1000] + + ) + +Element["" "R025" "R3" "68R" 70000 70000 0 -5000 0 100 ""] +( + Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"] + Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"] + ElementLine [10000 -5000 30000 -5000 2000] + ElementLine [30000 -5000 30000 5000 2000] + ElementLine [30000 5000 10000 5000 2000] + ElementLine [10000 5000 10000 -5000 2000] + ElementLine [0 0 10000 0 2000] + ElementLine [30000 0 40000 0 2000] + + ) + +Element["" "R025" "R2" "68R" 70000 80000 0 -5000 0 100 ""] +( + Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"] + Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"] + ElementLine [10000 -5000 30000 -5000 2000] + ElementLine [30000 -5000 30000 5000 2000] + ElementLine [30000 5000 10000 5000 2000] + ElementLine [10000 5000 10000 -5000 2000] + ElementLine [0 0 10000 0 2000] + ElementLine [30000 0 40000 0 2000] + + ) + +Element["" "ALF500" "D2" "1N4148" 150000 70000 -25000 0 1 100 ""] +( + Pin[0 0 8000 3000 8600 2000 "1" "1" "square"] + Pin[0 -50000 8000 3000 8600 2000 "2" "2" ""] + ElementLine [0 -16600 0 0 1000] + ElementLine [0 -50000 0 -33400 1000] + ElementLine [0 -16600 -8300 -33400 1000] + ElementLine [-8300 -33400 8300 -33400 1000] + ElementLine [8300 -33400 0 -16600 1000] + ElementLine [-8300 -16600 8300 -16600 1000] + + ) + +Element["" "ACY500" "R1" "47K" 110000 60000 0 4100 2 100 ""] +( + Pin[0 0 5500 3000 6100 3000 "1" "1" "square"] + Pin[0 -50000 5500 3000 6100 3000 "2" "2" ""] + ElementLine [0 -12500 0 0 1000] + ElementLine [0 -50000 0 -37500 1000] + ElementLine [-4100 -37500 -4100 -12500 1000] + ElementLine [-4100 -37500 4100 -37500 1000] + ElementLine [4100 -37500 4100 -12500 1000] + ElementLine [-4100 -12500 4100 -12500 1000] + + ) + +Element["" "RCY100" "X1" "32768_Hz" 75000 40000 -10000 5000 1 100 ""] +( + Pin[0 0 6000 3000 6600 3000 "1" "1" "square"] + Pin[0 -10000 6000 3000 6600 3000 "2" "2" ""] + ElementArc [0 -5000 10000 10000 90 360 1000] + + ) + +Element["" "pad_thru" "" "pad_thru" 120000 60000 -3938 -11811 0 100 ""] +( + Pin[0 0 6100 3937 6494 3500 "1" "1" ""] + ElementArc [0 0 4000 4000 0 360 1000] + + ) + +Element["" "pad_thru" "" "pad_thru" 100000 30000 -3938 -11811 0 100 ""] +( + Pin[0 0 6100 3937 6494 3500 "1" "1" ""] + ElementArc [0 0 4000 4000 0 360 1000] + + ) + +Element["" "pad_thru" "" "pad_thru" 100000 50000 -3938 -11811 0 100 ""] +( + Pin[0 0 6100 3937 6494 3500 "1" "1" ""] + ElementArc [0 0 4000 4000 0 360 1000] + + ) + +Element["" "ALF600" "D1" "1N4148" 140000 80000 -30000 0 1 100 ""] +( + Pin[0 0 8000 3000 8600 2000 "1" "1" "square"] + Pin[0 -60000 8000 3000 8600 2000 "2" "2" ""] + ElementLine [0 -20000 0 0 1000] + ElementLine [0 -60000 0 -40000 1000] + ElementLine [0 -20000 -10000 -40000 1000] + ElementLine [-10000 -40000 10000 -40000 1000] + ElementLine [10000 -40000 0 -20000 1000] + ElementLine [-10000 -20000 10000 -20000 1000] + + ) +Rat[170000 20000 0 170000 80000 0 ""] +Rat[170000 80000 0 170000 70000 0 ""] +Rat[75000 30000 0 75000 40000 0 ""] +Rat[70000 80000 0 70000 70000 0 ""] +Layer(1 "top") +( + Line[25000 20000 10000 20000 1000 2000 "clearline"] + Line[10000 20000 10000 10000 1000 2000 "clearline"] + Line[10000 10000 170000 10000 1000 2000 "clearline"] + Line[55000 70000 70000 70000 1000 2000 "clearline"] + Line[55000 80000 70000 80000 1000 2000 "clearline"] + Line[55000 20000 170000 20000 1000 2000 "clearline"] + Line[55000 30000 75000 30000 1000 2000 "clearline"] + Line[55000 40000 75000 40000 1000 2000 "clearline"] + Line[110000 70000 170000 70000 1000 2000 "clearline"] + Line[170000 40000 120000 40000 1000 2000 "clearline"] + Line[120000 40000 120000 60000 1000 2000 "clearline"] + Line[120000 60000 55000 60000 1000 2000 "clearline"] + Line[170000 30000 100000 30000 1000 2000 "clearline"] + Line[100000 30000 100000 50000 1000 2000 "clearline"] + Line[100000 50000 55000 50000 1000 2000 "clearline"] + Line[110000 80000 170000 80000 1000 2000 "clearline"] +) +Layer(2 "ground") +( +) +Layer(3 "signal2") +( +) +Layer(4 "signal3") +( +) +Layer(5 "power") +( +) +Layer(6 "bottom") +( +) +Layer(7 "outline") +( +) +Layer(8 "spare") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( + Text[10000 90000 0 100 "Vetinari's Clock v1.0" "clearline"] +) +NetList() +( + Net("CLKN" "(unknown)") + ( + Connect("CONN2-2") + Connect("D2-2") + Connect("R2-2") + ) + Net("CLKP" "(unknown)") + ( + Connect("CONN2-1") + Connect("D1-2") + Connect("R3-2") + ) + Net("GND" "(unknown)") + ( + Connect("CONN1-2") + Connect("D1-1") + Connect("D2-1") + Connect("U1-14") + ) + Net("RST" "(unknown)") + ( + Connect("CONN1-4") + Connect("R1-1") + Connect("U1-10") + ) + Net("TEST" "(unknown)") + ( + Connect("CONN1-3") + Connect("U1-11") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("U1-13") + Connect("X1-1") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("U1-12") + Connect("X1-2") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("R2-1") + Connect("U1-9") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("R3-1") + Connect("U1-8") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("U1-2") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("U1-3") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("U1-4") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("U1-5") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("U1-6") + ) + Net("unnamed_net10" "(unknown)") + ( + Connect("U1-7") + ) + Net("Vcc" "(unknown)") + ( + Connect("CONN1-1") + Connect("R1-2") + Connect("U1-1") + ) +) diff --git a/circuit_pth/vetinari.project b/circuit_pth/vetinari.project new file mode 100644 index 0000000..b99306c --- /dev/null +++ b/circuit_pth/vetinari.project @@ -0,0 +1,8 @@ +schematics vetinari.sch +output-name vetinari +elements-dir ~/gaf/libraries/luciani.org +elements-dir ~/gaf/libraries/patthoyts/footprints +elements-dir ~/gaf/libraries/knaak/footprints +elements-dir /usr/share/pcb/newlib +elements-dir /usr/share/pcb/pcblib-newlib + diff --git a/circuit_pth/vetinari.sch b/circuit_pth/vetinari.sch new file mode 100644 index 0000000..23b307b --- /dev/null +++ b/circuit_pth/vetinari.sch @@ -0,0 +1,194 @@ +v 20130925 2 +C 19800 62300 0 0 0 title-B.sym +C 29000 70000 1 270 0 crystal-1.sym +{ +T 29500 69800 5 10 0 0 270 0 1 +device=CRYSTAL +T 29300 69800 5 10 1 1 0 0 1 +refdes=X1 +T 29700 69800 5 10 0 0 270 0 1 +symversion=0.1 +T 29000 70000 5 10 0 0 0 0 1 +footprint=RCY100 +T 29300 69600 5 10 1 1 0 0 1 +value=32768 Hz +} +C 28800 68100 1 0 0 resistor-2.sym +{ +T 29200 68450 5 10 0 0 0 0 1 +device=RESISTOR +T 28900 68400 5 10 1 1 0 0 1 +refdes=R2 +T 29400 68400 5 10 1 1 0 0 1 +value=68R +T 28800 68100 5 10 0 1 0 0 1 +footprint=R025 +} +C 28800 67700 1 0 0 resistor-2.sym +{ +T 29200 68050 5 10 0 0 0 0 1 +device=RESISTOR +T 28900 67500 5 10 1 1 0 0 1 +refdes=R3 +T 28800 67700 5 10 0 0 0 0 1 +footprint=R025 +T 29400 67500 5 10 1 1 0 0 1 +value=68R +} +C 28300 70400 1 90 0 resistor-2.sym +{ +T 27950 70800 5 10 0 0 90 0 1 +device=RESISTOR +T 28600 71100 5 10 1 1 180 0 1 +refdes=R1 +T 28300 70700 5 10 1 1 0 0 1 +value=47K +T 28300 70400 5 10 0 0 0 0 1 +footprint=ACY500 +} +C 30900 66300 1 90 0 diode-1.sym +{ +T 30300 66700 5 10 0 0 90 0 1 +device=DIODE +T 31200 67000 5 10 1 1 180 0 1 +refdes=D2 +T 30900 66300 5 10 0 0 0 0 1 +footprint=ALF500 +T 30900 66600 5 10 1 1 0 0 1 +value=1N4148 +} +C 30200 66300 1 90 0 diode-1.sym +{ +T 29600 66700 5 10 0 0 90 0 1 +device=DIODE +T 29400 67000 5 10 1 1 180 0 1 +refdes=D1 +T 29100 66600 5 10 1 1 0 0 1 +value=1N4148 +T 30200 66300 5 10 0 1 0 0 1 +footprint=ALF600 +} +C 32700 68400 1 180 0 connector2-1.sym +{ +T 32500 67400 5 10 0 0 180 0 1 +device=CONNECTOR_2 +T 32700 67600 5 10 1 1 180 0 1 +refdes=CONN2 +T 32700 67700 5 10 0 0 0 0 1 +footprint=1x2PIN +T 32100 67300 5 10 1 1 0 0 1 +value=COIL +T 32700 68100 5 10 0 0 0 0 1 +net=CLKP:1 +T 32700 67900 5 10 0 0 0 0 1 +net=CLKN:2 +} +C 33400 68500 1 0 1 connector4-1.sym +{ +T 31600 69400 5 10 0 0 0 6 1 +device=CONNECTOR_4 +T 33400 70100 5 10 1 1 0 6 1 +refdes=CONN1 +T 32800 69900 5 10 1 1 0 0 1 +value=POWER +T 33400 68500 5 10 0 1 0 0 1 +footprint=1x4PIN +T 33400 69500 5 10 0 0 0 0 1 +net=Vcc:1 +T 33400 69200 5 10 0 0 0 0 1 +net=GND:2 +T 33400 68900 5 10 0 0 0 0 1 +net=TEST:3 +T 33400 68700 5 10 0 0 0 0 1 +net=RST:4 +} +C 23500 67300 1 0 0 MSP430G2231.sym +{ +T 27400 70700 5 10 1 1 0 6 1 +refdes=U1 +T 23900 70900 5 10 0 0 0 0 1 +device=MSP430G2x11IPW14 +T 23900 71100 5 10 0 0 0 0 1 +footprint=DIP-14-300 +} +C 23400 71900 1 0 0 vcc-1.sym +C 31400 65300 1 0 0 gnd-1.sym +N 29100 70000 28600 70000 4 +N 28600 70000 28600 69800 4 +N 28600 69800 27700 69800 4 +N 29100 69300 28600 69300 4 +N 27700 69400 28600 69400 4 +N 28600 69400 28600 69300 4 +N 27700 69000 31700 69000 4 +N 27700 68600 28400 68600 4 +N 28400 68600 28400 68700 4 +N 28400 68700 31700 68700 4 +N 31700 69300 31500 69300 4 +N 31500 65600 31500 70200 4 +N 30000 66300 31500 66300 4 +N 31000 68200 29700 68200 4 +N 28800 68200 27700 68200 4 +N 28800 67800 27700 67800 4 +N 29700 67800 30500 67800 4 +N 30500 67800 30500 67900 4 +N 30500 67900 31000 67900 4 +N 30000 67200 30000 67800 4 +N 30700 67200 30700 68200 4 +N 31500 70200 27700 70200 4 +N 23600 70200 23600 71900 4 +C 23100 67700 1 0 0 nc-left-1.sym +{ +T 23100 68100 5 10 0 0 0 0 1 +value=NoConnection +T 23100 68500 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 23100 68100 1 0 0 nc-left-1.sym +{ +T 23100 68500 5 10 0 0 0 0 1 +value=NoConnection +T 23100 68900 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 23100 68500 1 0 0 nc-left-1.sym +{ +T 23100 68900 5 10 0 0 0 0 1 +value=NoConnection +T 23100 69300 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 23100 68900 1 0 0 nc-left-1.sym +{ +T 23100 69300 5 10 0 0 0 0 1 +value=NoConnection +T 23100 69700 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 23100 69300 1 0 0 nc-left-1.sym +{ +T 23100 69700 5 10 0 0 0 0 1 +value=NoConnection +T 23100 70100 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 23100 69700 1 0 0 nc-left-1.sym +{ +T 23100 70100 5 10 0 0 0 0 1 +value=NoConnection +T 23100 70500 5 10 0 0 0 0 1 +device=DRC_Directive +} +N 23600 71500 31700 71500 4 +N 31700 71500 31700 69600 4 +N 28200 70400 28200 68600 4 +N 28200 71300 28200 71500 4 +T 29900 63200 15 10 1 0 0 0 1 +Vetinari's Clock Using Low Power MSP430 +T 33700 62400 15 10 1 0 0 0 1 +Pat Thoyts +T 33700 62700 15 10 1 0 0 0 1 +6 Dec 2014 +T 29900 62400 15 10 1 0 0 0 1 +1 +T 31400 62400 15 10 1 0 0 0 1 +1